Circuit for discriminating between received signals and method therefor

ABSTRACT

A circuit for discriminating between received signals and a method therefor are provided. The circuit includes a detector for detecting a peak signal based on the degree of correlation between a received signal and a reference signal and a generator for generating a discrimination signal showing that the received signal is a high definition signal if the peak signal is detected in a predetermined period and showing that the received signal is a signal of an analog broadcasting method if the peak signal is not detected in the predetermined period. This can prevent the improper operation of a receiver by automatically determining whether the received signal according to a channel selection is a high definition digital signal or an analog broadcast signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of reception, and moreparticularly, to a circuit for determining whether a received signal isa high definition signal or an analog broadcast signal.

[0003] 2. Description of the Related Art

[0004] Recently, in the United States, a test of a “Grand Alliance” (GA)advanced television (ATV) system which is a digital televisiontransmission system has been completed as a new television standardwhich can replace a conventional analog NTSC. The GA-ATV system,standardized by an advanced television system committee (ATSC) (GA-HDTVor GA-VSB), employs a vestigial side band (VSB) modulation method whichis a digital transmission method.

[0005] However, even with the start of HDTV broadcasts, the conventionalNTSC cannot help but coexist. A receiver must have a structure in whichit is possible to simultaneously watch the HDTV broadcasts and the NTSCTV broadcasts. Namely, since the same channel can be broadcast in eitherNTSC TV or HDTV, depending on the area, a structure in which it ispossible to watch the two types of broadcasts is necessary. In general,a simulcast receiver which receives an HDTV signal and an NTSC TV signalcan be comprised of a tuner, an HDTV signal processor and an NTSC TVsignal processor for separately processing the HDTV signal and the NTSCTV signal, and a display. Therefore, in order to display either the HDTVsignal or the NTSG TV signal using a single display, it is necessary todetermine whether the currently received signal is a HDTV signal or aNTSC TV signal. Also, in order to display whether the channel selectedby the user is the HDTV channel or the NTSC TV channel in the receiverreceiving the HDTV signal, a circuit for determining whether thecurrently selected signal is the HDTV signal or the NTSC TV signal isnecessary. cl SUMMARY OF THE INVENTION

[0006] It is an object of the present invention to provide a circuit fordetermining whether a received signal is a high definition digitalsignal or an analog broadcasting signal.

[0007] It is another object of the present invention to provide a methodof determining whether a received signal is a high definition digitalsignal or an analog broadcast signal.

[0008] To achieve the first object, a detector of a circuit fordiscriminating between received signals detects a peak signal based on adegree of correlation between a received signal and a reference signal.A generator shows that the received signal is a high definition signalhaving a predetermined digital signal format if the peak signal isdetected in a predetermined period and shows that the received signal isa signal of an analog broadcast method if the peak signal is notdetected in the predetermined time.

[0009] To achieve the second object, there is provided a method fordiscriminating whether a received signal is a high definition signalhaving a digital format or a signal of an analog broadcast method,comprising the steps of detecting a peak signal based on a degree ofcorrelation between a received signal and a reference signal andgenerating a discrimination signal showing that the received signal is ahigh definition signal if the peak signal is generated in apredetermined period and showing that the received signal is a signal ofan analog broadcast method if the peak signal is not detected in thepredetermined period.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above objects and advantages of the present invention willbecome more apparent by describing in detail a preferred embodimentthereof with reference to the attached drawings in which:

[0011]FIG. 1 is a block diagram showing an HD/NTSC simulcast receiver towhich the present invention is applied;

[0012]FIG. 2 is a detailed block diagram showing a channel decoder andan HD/NTSC discriminating circuit, shown in FIG. 1;

[0013]FIG. 3 illustrates a VSB transmission frame format; and

[0014]FIG. 4 is a representation of a field synchronizing signalsequence of a field synchronizing segment shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, a circuit for discriminating between different typesof received signals according to the present invention and a methodtherefor will be described with reference to the attached drawings.

[0016] In FIG. 1, a tuner 102 simultaneously receives an HDTV signal andan NTSC TV signal. In a buffer/demultiplexer 104, the HDTV signal or theNTSC TV signal provided through the tuner 102 is temporarily stored inthe buffer, demultiplexed by the demultiplexer, and is provided to anNTSC intermediate frequency (IF) amplifier 106 and an HD IF amplifier112.

[0017] The NTSC IF amplifier 106 amplifies an NTSC IF signal providedfrom the buffer/demultiplexer 104. The NTSC processor 108 demodulatesthe amplified NTSC IF signal to a baseband signal. A firstanalog-to-digital converter (ADC) 110 converts the demodulated analogNTSC signal into digital data and provides the result to a first inputport of a display processor 122.

[0018] The HD IF amplifier 112 amplifies the HD IF signal provided fromthe buffer/demultiplexer 104. A second ADO 114 converts the amplified HDIF signal into the digital data. A channel decoder 116 demodulates theHD IF signal converted into the digital data to the baseband signal,restores a segment synchronizing signal and a symbol clock from the datademodulated to the baseband signal and provides the restored segmentsynchronizing signal and symbol clock to an HD/NTSC discriminatingcircuit 200. The demodulated HD signal is in the form of a transportpacket. Therefore, a transmission decoder 118 analyses a transportpacket header from the transport packet and divides the transport packetinto a video stream and an audio stream based on the analyzed packetidentification (PID). A video decoder 120 decodes the video data fromthe video stream.

[0019] The HD/NTSC discriminating circuit 200 determines whether thereceived signal is the HDTV signal or the NTSC TV signal using thesegment synchronizing signal and the symbol clock provided from thechannel decoder 116 and provides a discriminating signal HDINTSC. Adisplay processor 122 selects either the NTSC TV signal provided from afirst ADC 110 or the HDTV signal provided from the video decoder 120according to the discriminating signal HD/NTSC, processes the selectedsignal as a signal suitable to be displayed, and provides the processedsignal to a digital-to-analog converter (DAC)/mixer 124.

[0020] The DAC/mixer 124 converts the data processed by the displayprocessor 122 into an analog image signal, generates an on screendisplay (OSD) signal as an example of caption information displayingwhether the currently received channel is a HDTV channel or a NTSC TVchannel based on the discriminating signal HD/NTSC provided by theHD/NTSC discriminating circuit 200, mixes the generated OSD signal withthe analog image signal, and displays the mixed signal through a display126. The caption information can be an on screen graphic (OSG) signal.

[0021] Here, a structure obtained by omitting parts from thebuffer/DEMUX 104 to the first ADC 110 from the simulcast receiver shownin FIG. 1 can be the structure of a receiver for receiving only an HDTVsignal.

[0022]FIG. 2 is a detailed block diagram of the channel decoder 116 andthe discriminating circuit 200 shown in FIG. 1. In FIG. 2, a digitalfrequency phase locked loop (DFPLL) circuit 128 of the channel decoder116 restores a carrier wave using a pilot signal included in the dataprovided from the second ADO 114, and demodulates the restored carrierwave into the baseband signal.

[0023] A matching filter 130 controls the symbol rate of the dataprovided from the DFPLL circuit 128 in order to remove signal distortionand aliasing from the demodulated baseband signal. Namely, the matchingfilter 130 controls the symbol rate 2fs of the data provided from theDFPLL circuit 128 to be a symbol clock fs.

[0024] An NTSC rejection filter 132 removes the component of the NTSC TVsignal included in the HDTV signal provided by the matching filter 130since the NTSC TV signal operates as an interference when the NTSC TVsignal coexists in the HDTV channel.

[0025] A symbol clock restorer 134 restores the symbol clock in responseto the output of the matching filter 130 and the segment synchronizingsignal provided from the segment synchronizing signal detector 136 andapplies a sampling clock having a frequency 2fs two times larger thanthat of the symbol clock to the second ADO 114 shown in FIG. 1. Thesymbol clock fs restored by the symbol clock restorer 134 is provided toother blocks for processing the digital signal though not shown in thedrawings as well as the matching filter 130 and the HD/NTSCdiscriminating circuit 200.

[0026] The segment synchronizing signal detector 136 detects the segmentsynchronizing signal from the output of the matching filter 130. Namely,the segment synchronizing signal detector 136 inputs the data controlledto have the symbol rate fs provided from the matching filter 130,obtains correlation values in units of four symbols, accumulates theobtained correlation values in units of a segment, and generates thesegment synchronizing signal in a position in which a maximumaccumulated correlation value is detected in every data segment sincethe accumulated correlation value of each segment has the maximum valueduring four segment synchronizing symbol sections.

[0027] An equalizer 138 updates and equalizes coefficients of a filterin the equalizer using a known sequence inserted in the fieldsynchronizing segment in order to remove a multipath distortion passingthrough the transmission channel.

[0028] A Trellis-coded modulation (TCM) decoder 140 Trellis-decodes theoutput of the equalizer 138. A forward error correction (FEC) decoder142 de-interleaves the Trellis decoded data, error-correction-decodesand de-randomizes the de-interleaved data, and provides the data to thetransmission decoder 118 shown in FIG. 1.

[0029] A first input port of a 511 pseudo number (PN) correlator 204 ofthe HD/NTSC discriminating circuit 200 provided by the present inventionis connected to the output port of the matching filter 130. A secondinput port thereof is connected to the output port of a first referencesignal generator 202. A first input port of a 63PN correlator 214 isconnected to the output port of the matching filter 130. A second inputport thereof is connected to a second reference signal generator 212.

[0030] A first input port of a first peak detector 206 is connected tothe output port of the 511PN correlator 204. A first reference valueREF1 is input to a second input port thereof. A first input port of asecond peak detector 216 is connected to the output port of the 63PNcorrelator 214. A second reference value REF2 is input to a second inputport thereof. An enable port of a first confidence counter 208 isconnected to the output port of the first peak detector 206. A clockport thereof is connected to the output port of the segmentsynchronizing signal detector 136. An output port thereof is connectedto a first decision circuit 210. An enable port of a second confidencecounter 218 is connected to the output port of the second peak detector216. A clock port thereof is connected to the output port of the symbolclock restorer 134. An output port thereof is connected to the outputport of a second decision circuit 220. A discrimination signal generator222 can be comprised of a multiplier or an AND gate. First and secondinput ports thereof are respectively connected to the output ports ofthe first and second decision circuits 210. An output port thereof isconnected to each control port of the display processor 122 and theDAC/mixer 124.

[0031] The operation of the HD/NTSC discriminating circuit 200 will bedescribed with reference to FIGS. 3 and 4. In FIG. 3, the HDTV signalprovided from the matching filter 130, i.e., the VSB data is input toeach first input port of the 5I1PN correlator 204 and the 63PNcorrelator 214.

[0032] Here, a VSB data frame is comprised of two fields as shown inFIG. 3. Each field is comprised of one field synchronizing segment and312 data segments. Each data segment is comprised of the segmentsynchronizing signal of four symbols and 828 data symbols. The segmentsynchronizing signal is inserted into a digital data stream having 8levels in the front of the field synchronizing segment and each datasegment. The segment synchronizing signal has a uniform pattern in whichfour symbols have a signal level of “+5, −5, −5, and +5”. The remainingdata of the data segment are randomly comprised of an arbitrary signallevel among eight levels (±1, ±3, ±5, and ±7).

[0033] Field synchronizing signal sequences FIELD SYNC #1 and FIELD SYNC#2 showing the beginning of fields are inserted into field synchronizingsegments which are the first segments of the respective fields. Namely,as shown in FIG. 4, the field synchronizing segment is comprised of 832symbols. The segment synchronizing signal is positioned in the firstfour symbols. A 511 pseudo number (511PN) is positioned in the next 511symbols. Three 63PNs are positioned in the next 189 symbols. Theadditional information is provided for the remaining 128 symbols. Here,since the 511PN is a predetermined signal sequence represented by the +5and −5 level, it is used in a signal processing block using a knownsequence such as equalization. In the second 63PN among the three 63PN,phases are inverted alternately in every field. The field synchronizingsignal sequence showing the beginning of the field having the formatshown in FIG. 4 is inserted into the first segment of every field. Thefield synchronizing signal sequence always has a uniform pattern.

[0034] The first reference signal generator 202 generates a pseudorandom number in which the length of a reference signal is 511 (a 511 PNreference signal). Namely, the first reference signal generator 202locally and repeatedly generates the same signal as the 511 PN includedin the field synchronizing signal sequence shown in FIG. 3. The secondreference signal generator 212 generates a pseudo random number in whichthe length of a reference signal is 63 (a 63PN reference signal).Namely, the second reference signal generator locally and repeatedlygenerates the same signal as the 63PN included in the fieldsynchronizing signal sequence. In the present invention, the firstreference signal generator 202 and the second reference signal generator212 are separately constructed in order to facilitate description.However, the 511 PN reference signal and the 63PN reference signal maybe generated from single reference signal generator.

[0035] The 511 PN reference signal and the 63PN reference signalgenerated from the first reference signal generator 202 and the secondreference signal generator 212 are respectively provided to the secondinput ports of the 511 PN correlator 204 and the 63PN correlator 214.Therefore, the 511 PN correlator 204 obtains the correlation value ofthe 511 PN by accumulating the correlation values of between the VSBdata and the 511 PN reference signal in units of the 511 symbol. Thefirst peak detector 206 detects whether the correlation value of the 511PN provided from the 511 PN correlator 204 is no less than the firstreference value REF1 and provides the first peak signal. The first peaksignal is detected in each field.

[0036] The 63PN correlator 212 obtains the correlation value of the 63PNby accumulating the correlation values of between the VSB data and the63PN reference signal in units of 63 symbols. The second peak detector216 detects whether the correlation value of the 63PN provided from the63PN correlator 212 is no less than the second reference value REF2 andprovides the second peak signal. The second peak signal is alternatelydetected in every field two or three times. This is because phases areinverted alternately in every field in the second 63PN among the three63PNs.

[0037] At this time, the peak value is shown where the 511 PN signal andthe 63PN signal included in the field synchronizing signal sequence arepositioned and a value of almost “0” in places other than the fieldsynchronizing signal sequence. Here, in order to simplify hardware, theS11PN correlator 202 and the 63PN correlator 212 can respectively detectthe correlation value of the 63PN and the correlation value of the 511PN by comparing only the sign bit of the input VSB data with the 63 PNreference signal and the 511 PN reference signal, respectively.

[0038] The first confidence counter 208 verifies the confidence of thepeak value detected by the first peak detector 206 using the segmentsynchronizing signal provided by the segment synchronizing signaldetector 136. In the case of the HDTV signal, the first peak signal isprovided by the first peak detector 206 whenever the segmentsynchronizing signal is generated 313 times. Therefore, the firstconfidence counter 208 receives the first peak signal as an enablesignal when the first peak signal is detected by the first peak detector206 and counts the segment synchronizing signal generated by the segmentsynchronizing signal detector 136. The first confidence counter 208counts the 313 segment synchronizing signals and provides a logic “high”signal to the first decision circuit 210 when the first peak signal isprovided from the first peak detector 206. The second confidence counter218 verifies the confidence of the peak value detected by the secondpeak detector 216. In the case of the HDTV signal, as shown in FIG. 4,the two second peak signals with respect to the first and third 63PNsamong the continuous three 63PNs are provided by the second peakdetector 216 in every field. Therefore, the second confidence counter218 receives the beginning second peak signal of the second peakdetector 216 as an enable signal, counts 126 symbol clocks generated bythe symbol clock restorer 134, and provides the logic “high” signal tothe second decision circuit 220 when the next second peak signal isinput. Here, a distance between the first symbol of the first 63PN tothe first symbol of the third 63PN is 126 symbols.

[0039] The first and second decision circuits 210 and 220 determine thelogic “high” signals continuously provided a predetermined number oftimes by the first and second confidence counters 208 and 218 to be theHDTV signals and provide the first and second decision signals of thelogic “high”. Namely, the first and second decision circuits 210 and 220observe the output signals of the first and second confidence counters208 and 218 for a certain time, determine whether periodicity exists,and determine whether the output signals are the HDTV signals or theNTSC TV signals. In the case of the HDTV signal, there is continuousperiodicity.

[0040] The multiplier of the discriminating signal generator 222multiplies the output of the first decision circuit 210 by the output ofthe second decision circuit 220 and provides the discrimination signalHD/NT.SC. Namely, the discrimination signal generator 222 provides adiscrimination signal of logic “high” showing that the output signalsare the HDTV signals when periodicity is detected simultaneously in boththe first and second decision circuits 210 and 220. When there is noperiodicity is in either of the two circuits 210 and 220, adiscrimination signal of logic “low” showing that the output signals arethe NTSC TV signal is provided.

[0041] In FIG. 2, two channels exist for the confidence of thediscrimination circuit. However, one channel may exist. Also, thepresent invention can be applied to a receiver for receiving a digitalterrestrial wave HDTV signal to be broadcast as well as the simulcastreceiver which can simultaneously receive the NTSC TV signal and theHDTV signal. Namely, in the HDTV receiver, the channel selected by auser indicating whether the selected channel is a HDTV channel or a NTSCchannel is displayed by a caption information according to the HD/NTSCdiscrimination signal. In the present invention, the NTSC TV signal andthe HDTV signal of a VSB modulation method are respectively described asan example of the signal of the analog broadcasting method and anexample of the high definition signal. A standard definition (SD) signalcan be included in the high definition signal.

[0042] As mentioned above, according to the present invention, it ispossible to prevent improper operation of the receiver since thereceived signal according to channel selection is the high definitionsignal or the signal of the analog broadcast method, thus meeting theneeds of consumers.

What is claimed is:
 1. A circuit for discriminating between receivedsignals, comprising: means for detecting a peak signal based on acorrelation degree between a received signal and a reference signal; andmeans for generating a discrimination signal for showing that thereceived signal is a high definition signal having a predetermineddigital signal format if the peak signal is detected in a predeterminedperiod and showing that the received signal is a signal of an analogbroadcast method if the peak signal is not detected in the predeterminedperiod.
 2. The circuit of claim 1, wherein the detecting meanscomprises: a correlator for obtaining said correlation degree betweensaid received high definition signal and said reference signal andproviding a correlation value; and a peak detector for providing saidpeak signal when the correlation value is larger than the referencevalue.
 3. The circuit of claim 2, wherein the correlator detects saidcorrelation degree between a sign bit of said received high definitionsignal and said reference signal.
 4. The circuit of claim 1, wherein thereference signal is in the same signal sequence as a 511 pseudo number(PN) of a field synchronizing signal sequence of a VSB signal.
 5. Thecircuit of claim 4, wherein the generating means generates thediscrimination signal showing that the received signal is said highdefinition signal when the peak signal is continuously provided apredetermined number of times from the detecting means in a fieldperiod.
 6. The circuit of claim 1, wherein the reference signal is inthe same signal sequence as a 63PN of a field synchronizing signalsequence of a VSB signal.
 7. The circuit of claim 6, wherein thegenerating means generates said discrimination signal showing that thereceived signal is said high definition signal when the peak signal isprovided from the detecting means by a distance of a predeterminedsymbol and when the peak signal generated by the distance of thepredetermined symbol is continuously provided a predetermined number oftimes in a field period.
 8. The circuit of claim 1, wherein thedetecting means comprises: a first correlator for obtaining saidcorrelation degree between said received high definition signal and afirst reference signal and providing a first correlation value; a secondcorrelator for obtaining a correlation degree between the highdefinition signal and a second reference signal and providing a secondcorrelation value; a first peak detector for providing a first peaksignal when the first correlation value is larger than a first referencevalue; and a second peak detector for providing a second peak signalwhen the second correlation value is larger than a second referencevalue.
 9. The circuit of claim 8, wherein the first and secondcorrelators respectively obtain correlation degrees between a sign bitof a high definition signal and first and second reference signals andprovide first and second correlation values.
 10. The circuit of claim 8,wherein the first reference signal is in the same signal sequence as the511PN signal and the second reference signal is in the same signalsequence as the 63PN signal.
 11. The circuit of claim 8, wherein thegenerating means comprises: a first periodicity detector for detectingperiodicity of the first peak signal; a second cycle detector fordetecting periodicity of the second peak signal; and a logic circuit forgenerating the discrimination signal for showing that said receivedsignal is the high definition signal when periodicity is detected in thefirst and second periodicity detectors and that the received signal is asignal of the analog broadcast method when no periodicity is detected ineither of the two detectors.
 12. The circuit of claim 8, wherein thegenerating means comprises: a first confidence counter for counting thesegment synchronizing signal and providing a first detection signal whenthe first peak signal is detected in a field period; a second confidencecounter for counting a symbol clock and providing a second detectionsignal when the second peak signal is detected by a distance of apredetermined symbol; a first decision circuit for generating a firstdecision signal of active state when the first detection signal iscontinuously provided a predetermined number of times; a second decisioncircuit for generating a second decision signal of active state when thesecond detection signal is continuously provided a predetermined numberof times; and a logic circuit for generating the discrimination signalshowing that said received signal is the high definition signal when thefirst and second decision signals are all active states and showing thatthe received signal is a signal of the analog broadcast method wheneither of the two decision signals is not active state.
 13. The circuitof claim 1, wherein the receiver is a simulcast receiver, comprising: atuner for receiving said high definition signal having a predetermineddigital format and a signal of an analog broadcast method; a firstsignal processor for demodulating said high definition signal providedfrom the tuner to a baseband signal and detecting a segmentsynchronizing signal and a symbol clock from a demodulated signal; asecond signal processor for demodulating a signal of an analog broadcastmethod provided from the tuner to a baseband signal; and a display forselecting either the output signal of the first signal processor or ifthe output signal of the second signal processor according to thediscrimination signal and processing the selected output signal to asignal suitable for displaying.
 14. The circuit of claim 1, wherein thereceiver is a high definition receiver, comprising: a tuner forreceiving said high definition signal having a predetermined digitalformat; a channel decoder for demodulating said received high definitionsignal to a baseband signal and detecting a segment synchronizing signaland a symbol clock from a demodulated signal; and a display processorfor displaying whether the channel selected by a user is a highdefinition TV channel or a TV channel of an analog broadcast method as acaption data according to the discrimination signal.
 15. A method fordiscriminating whether a received signal is a high definition signalhaving a digital format or a signal of an analog broadcast method,comprising the steps of: (a) detecting a detection signal based on acorrelation degree between a received signal and a reference signal; and(b) generating a discrimination signal showing that the received signalis a high definition signal if the detection signal is generated in apredetermined period and showing that the received signal is a signal ofan analog broadcast method if the detection signal is not generated inthe predetermined period.
 16. The method of claim 15, wherein the step(a) comprises the steps of: (a1) providing a correlation value byobtaining said correlation degree between the received high definitionsignal and the reference signal; and (a2) providing said detectionsignal when the correlation value is larger than a reference value. 17.The method of claim 16, wherein the correlation degree between a signbit of the received high definition signal and the reference signal isdetected in the step (a1).
 18. The method of claim 15, wherein thereference signal is in the same signal sequence as the 511 PN of a fieldsynchronizing signal sequence of a VSB signal.
 19. The method of claim18, wherein the discrimination signal showing that the received signalis the high definition signal when the detection signal is continuouslyprovided a predetermined number of times in a field period in the step(a) is generated in the step (b).
 20. The method of claim 15, whereinthe reference signal is in the same signal sequence as the 63PN of afield synchronizing signal sequence of a VSB signal.
 21. The method ofclaim 20, wherein the discrimination signal showing that the receivedsignal is the high definition signal when the detection signal isgenerated by a distance of a predetermined symbol and when the detectionsignal generated by the distance of the predetermined symbol is provideda predetermined number of times in a field period in the step (a) isgenerated in the step (b).